Tecnologie per lo sviluppo di dispositivi a stato solido per applicazioni ad alta frequenza e larga banda

Abstract

In this work we present the optimization of Schottky contact for the fabrication of high electron mobility transistor with the intention of employing these devices for high frequency and high power applications. In order to increase the performances of the devices, it is possible to improve the material characteristics or to act on the devices process. We used GaAs and GaN substrates because of their better characteristics compared to Si and in particular because of the high electron mobility, the high break-down field, high bandgap and high thermal conductivity (GaN). Based on theory, the RF performances such as cut-off frequency and maximum oscillation frequency, are directly connected to the gate characteristics and closer to the parasitic capacitance and resistance. We can write the mathematical formula for the correlation of these parameter: 𝑓𝑇=𝑔𝑚2𝜋𝐶𝐺𝑆 𝑓𝑀𝐴𝑋=𝑓𝑇2 𝑟1+𝑓𝑇𝜏3 𝐶𝐺𝑆∝ 𝐿𝐺 The gate capacitance is directly connected with the gate length and the smaller is this capacitance, the higher are the 𝑓𝑇 and 𝑓𝑀𝐴𝑋. Also the gate parasitic resistance has a bad influence on the RF performances and for this reason it is necessary to fabricate the gate with short length but large section in order to decrease the contact resistance 𝑅𝐺; we fabricated T-shape gate with 𝐿𝐺=0.25 𝜇𝑚 and large gate head. We used two different processes to fabricate the gate of the HEMT devices on GaN or GaAs with the aim to optimize the performances. Both the processes require the use of the electron beam lithography (EBL) because of the necessity to have high resolution in order to obtain small gate lengths. We briefly describe the two different processes. With respect to GaAs, the gate has been fabricated by using a single step of electron beam lithography; thanks to a trilayer of resist with different sensitivity, we are able to reproduce a T-shape for the gate. The process also consists of others steps such as the wet etching used for double recess, the evaporation and lift-off process. The optimization of the gate contact is consisted of the optimization of the lithography in term of doses, kind of resist and spin coating, dimension of the gate but also the optimization of chemical solution and heterostructures for the recess and the optimization of e-beam evaporation in term of improvement of the evaporation system. Thanks to these solutions we obtained low parasitic capacitances, low gate contact resistances, a good profile for the gate and good performances in term of RF and power characterizations. With respect to GaN, we used a double step of electron beam lithography, the first one to fabricated the gate-―foot‖ and the second one to fabricated the gate-―head‖; we used a bilayer and a trilayer of resist with different sensitivity to fabricate respectively the gate-―foot‖ and the gate-―head‖. The optimization of the gate contact for GaN is consisted of the optimization of the lithography in term of resist, doses, gate dimension, profile and spin coating. The others steps, that are used to the fabrication of the Schottky contact, are dry etch of silicon nitride, annealing of the gate-―foot‖ evaporation and lift-off process; in order to optimize the Si3N4 dry etch we tried to use different process with CF4/O2 or SF6 and different condition for the etch. The optimization of the annealing is consisted of the optimization of time and temperature of the process. Thanks to these solutions we obtained low parasitic capacitances and resistances, a good profile for the gate and good RF performances with fT=46 GHz and fmax=92 GHz.