Design, construction and tests of a high resolution, high dynamic range time to digital converter

Abstract

The needs of future High Energy Physics (HEP) experiments require the use of time measurements systems with remarkable benefits in terms of resolution, dynamic range and high operating frequency. This thesis is focused on the development and evaluation of high resolution and long range Time to Digital Converter (TDC) architectures suitable for the measurement of ~100 ns time intervals, ~100 ps resolution and MHz repetition rate in the context of the detectors of the KLOE experiment. The KLOE experiment has been designed in order to record e+e- collisions at DAΦNE, the ϕ-factory at the Laboratori Nazionali di Frascati. The thesis work is aimed to the specific requirements of the HEP experimental environment; nevertheless, it is also useful in many applications of science and industry where high resolution time measurements are required. Different configurations of tapped delay lines are widely used to measure nanosecond time intervals both in ASIC and FPGA devices. I designed and built a daughter board hosting the Virtex-5 FPGA from Xilinx, to test two different TDC architectures. Both TDC approaches use the classic Nutt method based on the two stage interpolation within the system clock cycle. The fine measurement of the short intervals have been performed by means of two different methods. The delay elements exploit either general purpose FPGA’s resources, like logic element, or special purpose resources, like dedicated carry logic. In the Virtex-5, these chain structures provide short predefined routes between identical logic elements. They are ideal for TDC delay chain implementation. The first architecture uses carry chain delays, while in the second one a differential tapped delay line is used. On the TDC Tester board two high stability oscillators, have been installed in order to compare their performances. The oscillators contain an internal voltage regulator for improved stability and noise performance. The Tester daughter board is hosted by a VME module which allows us to test and read-out the TDC via an embedded microprocessor. In this thesis I show the board and FPGA architectures together with experimental results. The performance of the TDCs was examined over the temperature range from 25°C to 75°C. The carry chain delay line TDC architecture seems to be the best one. The resolution values obtained are well fitting the needs of the time measurements of the KLOE experiment. In fact, in the KLOE experiment, the dynamic range is defined by the kinematics of kaon decays (the KL meson lifetime is about 50 ns); so the range of measurement needed is about 200-300 ns. In this range the carry chain delay line TDC shows a very good resolution of about 20 ps. Furthermore, the range of measurement of this kind of TDC is not limited to that value, but can easily extend until 20 μs with a time resolution below 35 ps. The time resolution increases of about 0.18 ps/°C; in fact for a 100 ns time interval measurements, it is between 17 ps (at 25°C) and 26 ps (at 75°) for a 50°C temperature shift. Moreover such a TDC is virtually dead time free; it implies its use in high trigger rate environment like Super B Factories where the estimated trigger rate is about 150 KHz at a luminosity of 1036 cm-2 s-1.